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-- Company: 
-- Engineer: 
-- 
-- Create Date:    19:58:38 11/28/2014 
-- Design Name: 
-- Module Name:    registers - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE ieee.numeric_std.ALL; 

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity registers is
    Port ( --en : in  STD_LOGIC;
			  clk : in STD_LOGIC;
           rs1 : in  STD_LOGIC_VECTOR (3 downto 0);
           rs2 : in  STD_LOGIC_VECTOR (3 downto 0);
           rd : in  STD_LOGIC_VECTOR (3 downto 0);
           datain : in  STD_LOGIC_VECTOR (15 downto 0);
           dataOut_1 : out  STD_LOGIC_VECTOR (15 downto 0);
			  reg7 : out STD_LOGIC_VECTOR (15 downto 0);
			  reg_output_option : in STD_LOGIC_VECTOR(3 downto 0);
           dataOut_2 : out  STD_LOGIC_VECTOR (15 downto 0));
end registers;

architecture Behavioral of registers is

--signal r0: STD_LOGIC_VECTOR(15 downto 0);
--signal r1: STD_LOGIC_VECTOR(15 downto 0);
--signal r2: STD_LOGIC_VECTOR(15 downto 0);
--signal r3: STD_LOGIC_VECTOR(15 downto 0);
--signal r4: STD_LOGIC_VECTOR(15 downto 0);
--signal r5: STD_LOGIC_VECTOR(15 downto 0);
--signal r6: STD_LOGIC_VECTOR(15 downto 0);
--signal r7: STD_LOGIC_VECTOR(15 downto 0);

signal T: STD_LOGIC_VECTOR(15 downto 0);
signal IH: STD_LOGIC_VECTOR(15 downto 0);
signal SP: STD_LOGIC_VECTOR(15 downto 0);
type REG is array (0 to 15) of STD_LOGIC_VECTOR(15 downto 0);
signal R : REG;

--t:9, ih:10, sp:11; null:15

begin

	process(clk)
	variable state	: integer range 0 to 1 := 0;
	--variable num : integer range 0 to 15;
	begin
		if clk'event and clk = '1' then
			case state is
			when 0=> --write
				if rd /= "1111" then
					--num := 
					R(TO_INTEGER(unsigned(rd(3 downto 0)))) <= datain;
				end if;
				state := 1;
			when 1=>--read
				if rs1 /= "1111" then
					dataOut_1 <= R(TO_INTEGER(unsigned(rs1(3 downto 0))));
				end if;--return 0 when reg number is 1111?
				if rs2 /= "1111" then
					dataOut_2 <= R(TO_INTEGER(unsigned(rs2(3 downto 0))));
				end if;
				state := 0;
			end case;
		end if;
		reg7 <= R(TO_INTEGER(unsigned(reg_output_option)));
	end process;

end Behavioral;

